digital lab report 6

| January 13, 2016

 

 

 

 

 

 

 

 

 

 

EET 205

Digital Electronics

 

 

Lab # 6

Sequential logic:

Flip-flops

 

 

 

 

“Almost all new ideas have a certain aspect of foolishness when they are first produced.”

 

–Alfred North Whitehead
Objectives:

To understand sequential logic and its applications in digital systems.

 

 

Exercise 1. Discrete Flip-Flop

Build the flip-flop described in the lecture from discrete NAND gates:

 

Connect the outputs to two LEDs of the Logic Monitor and the two inputs to two of the Logic Switches (set both switches high). What is the state of the outputs when you first power up the circuit? Try it several times. Is it consistent? Momentarily bring input A low. Does the output change? If not, try bringing input B momentarily low. Does it change now?

 

For whichever input changed the output, try bringing it momentarily low again several times. Does the output change? Try bringing the other input momentarily low. Does it change now? Repeat the sequence several times until you have a good feeling for what is happening. Discuss the properties of this setup in your report.

 

Leave your flip-flop set up; you will need it for a later exercise.

 

Exercise 2. JK Flip-flop
Go on the web and find the data sheet for a 74LS76A Dual Edge-triggered JK flip-flop, then wire up ½ of the chip (i.e., either one of the two JKs on the chip).

Connect J and K to two unused logic switches. Clock the circuit with pulses from the “NC” contact of one of the debounced pushbuttons, with a pull-up resistor tied to 5V.
(Ask your instructor or TA if you’re not sure how to connect this, or Google “pull-up”)

Try all four combinations of J and K (JK=00; JK=01; JK=10; JK=11), all with the ~PRESET and ~RESET inputs held high. ( ß This is important.)

Write out a truth table. How does it compare with the one given in the data sheet?

 

Does it clock on the negative-going edge (when the button is released) or the positive one (when the button is pressed down)?

 

What happens when you bring the ~RESET pin low? What about ~PRESET?
(Connect these to two other logic switches to be able to control them.)

 

Exercise 3. Divide-by-4

Now cascade the two flip-flops in the package, as shown. (The two flip-flops work identically, so you can choose either of them to be “first” as long as you remember which is which and connect the inputs accordingly.) It can be helpful to write down the pin numbers on the schematic below, to help you know which pins to connect. (Use the information from the datasheet to determine which pins do what.) Note that the “+5” is used as a logic input here; you will still need to connect power and ground, as always.

 

Display the states of the two outputs, Q, on LED indicators. What should happen on each flip-flop when both inputs, J and K, are tied high (look at the truth table)?

 

Clock it from one of the debounced pushbuttons several times and convince yourself that it is a divide-by-4 circuit, and that it counts in binary through the sequence:
0, 1, 2, 3, 0, 1, 2, 3, 0, 1 etc.
(The output from the left flip-flop is the lowest bit – the ones’ place.)

 


Exercise 4. Switch Debouncing

Instead of clocking the divide-by-4 from one of the debounced pushbuttons, clock it from the following circuit: (Use the pushbutton switches provided for this lab; do not use the “debounced pushbuttons” on the CADET II trainer).

 

Clock your counting circuit several times with the switch.

Does it count in the normal way? What is going on?

 

The problem with the above circuit is that normal (non-debounced) switches are “noisy”. When they are pressed or released, the contacts do not always connect and disconnect cleanly, and several pulses can be transmitted for a single press of the switch. (This is referred to as contact bounce, or clock bounce when such a circuit is used as a clock input.)

 
You can fix this using the original flip-flop circuit that you saved from Exercise 1. Modify it in the following way:

(Use a SPDT switch, located in the lower right part of the CADET II trainer.
If you’re not sure how to wire it, ask your instructor or TA.)

 

Does it work properly now? This is how the switches on your training board are “debounced.”

 

Keep your debouncing circuit set up for the rest of the lab.

 

Exercise 5. D-type (“Data”) Flip-flop

Remove the 74LS76 and replace it with a 74LS74 dual D flip-flop. (You’ll have to look up the pinouts for this one, too.) Wire up one of the D’s inside; there are two.

 

 

This device also has “~PRESET” and “~RESET” pins. Use the Function table in the data sheet you found to set these to the right values.

 

Try changing the input and clocking it across to the output (use your debounced switch for this). Does it clock through on the rising edge or the falling edge?

 

Try changing the Preset and clear (separately), and then toggling the input and clock. Do the Preset and/or Clear inputs override the D input and/or the clock?

 

Next, connect  to D to make a toggling flip-flop, as in the circuit below.
(Use your debounced input from above to clock it, not a simple switch as shown.)
Note that the switch is only connected to the CLK input; it does not connect to the wire between ~Q and D.

Clock it several times to see what it does.

 

 

Extra credit:

 

Finally, wire up the synchronous divide-by-three circuit shown below.

Can you figure out how it works? Describe how it works in your lab writeup. For full credit, draw a timing diagram and describe what the output duty cycle is, given a 50% duty cycle input. (You may want to simulate this in MultiSim, or you could analyze the circuit, clock-by-clock.)

 

End of Lab 5.

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Discuss at least three very important characteristic of differential amplifiers. What do the terms inverting and non-inverting mean in the context of amplifiers? Calculate the ideal IT, IE, Vc for the differential amplifier shown in the diagram

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